1. Field of the Invention
The present invention relates to the field of composite circuits integrating both a digital part and an analog part. The present invention more specifically aims at improving the isolation between the respective power supplies of the analog and digital parts of the integrated circuit.
2. Discussion of the Related Art
FIG. 1 very schematically shows an example of a composite circuit in CMOS technology. In an integrated circuit 1, the MOS transistors are distributed in blocks 2, 3, respectively corresponding to the digital and analog parts of the circuit. Analog block 2 and digital block 3 are separated from each other by an area 4. The integrated circuit, generally mounted on a printed circuit (not shown), is connected to supply terminals, for example, a positive terminal Vdd and a ground terminal GND. Analog block 2 and digital block 3 are supplied separately, that is, by means of different leads of the integrated circuit.
In FIG. 1, the different parasitic inductances and resistors of the package, associated with the power supply of the different components of the analog and digital blocks, have been modelled. Power to an analog component is provided, from supply line Vdd of the printed circuit via a parasitic inductance Lap in series with a parasitic resistor Rap, and this component is connected to ground GND of the printed circuit, also via a parasitic resistor Ran and a parasitic inductance Lan. Similarly, power to a digital component is provided, from line Vdd via a parasitic inductance Lnp in series with a parasitic resistor Rnp, and this component is connected to ground GND via a parasitic resistor Rnn in series with a parasitic inductance Lnn.
These parasitic inductances and resistors essentially correspond to the wire link between a pad of the integrated circuit chip and the corresponding lead, to this lead, and to the connection between the lead and the support of the integrated circuit package, currently, a printed circuit.
For each switching of a MOS transistor of the digital block, a parasitic pulse of the supply current occurs, and a noise voltage varying as L.di/dt+Ri, where L and R correspond to the parasitic inductance and resistance of the connection involved, is reflected on the power supply. It is generally desired, in a composite circuit, to avoid having this noise corrupt the analog part of the circuit and alter its operation.
Further, in a composite circuit, the isolation between the digital and analog grounds is delicate, especially when the substrate is relatively strongly conductive (a few ohms per centimeter).
A first conventional solution to improve the isolation between the digital and analog power supplies is to separate blocks 2 and 3 from the integrated circuit as much as possible. The resistance of separation area 4 is thus increased. Such a solution has the obvious disadvantage of increasing the circuit bulk.
FIG. 2 schematically illustrates a second conventional solution to improve the isolation between the digital and analog supplies of a composite circuit. FIG. 2 schematically shows a cross-sectional view of an integrated circuit in its central region 4 of separation between analog block 2 and digital block 3. As an example, the case of a circuit in which a P-type epitaxial layer 10 is formed on a P-type silicon wafer 11 has been considered. Epitaxial layer 10 forms the "substrate" in which MOS transistors or wells containing MOS transistors are formed. Still as an example and for clarity, a single MOS transistor, respectively 12, 13, of each block 2, 3, has been shown. These are P-channel transistors made in N-type wells 14, 14'. On the analog side, a contact 15, formed in a heavily-doped (N.sup.+) area 21, itself formed in well 14, is connected to potential Vdd (via parasitic inductance Lap and parasitic resistor Rap). On the digital side, a contact 15' formed on a heavily-doped (N.sup.+) area 21', itself formed in well 14', is connected to potential Vdd (via parasitic inductance Lnp and parasitic resistor Rnp).
FIG. 2 also shows contacts 24, 24' used to bias substrate 10, respectively, in blocks 2 and 3. These contacts are formed on heavily-doped (P.sup.+) areas, respectively 25 and 25'. Contact 24 is connected to the analog ground (not shown) of block 2, and thus to ground GND of the integrated circuit via parasitic inductance Lan and parasitic resistor Ran (FIG. 1). Similarly, contact 24' is connected to the digital ground (not shown) of block 3, and thus to ground GND of the integrated circuit via parasitic inductance Lnn and parasitic resistor Rnn (FIG. 1). The presence of contacts 24 and 24' enables substrate 10 to be equipotential and avoids the occurrence of latchup problems. Any potential variation on contact 24' or on contact 15', originating from a switching of digital block 3, generates noise on contact 24 via substrate 10 which forms a direct parasitic coupling path between the respective grounds of the digital and analog parts.
To improve the isolation between the analog and digital supplies for a given spacing between blocks 2 and 3, a well 16 of type opposite to that of epitaxial layer 10 is provided along the entire substrate length in area 4. In the example shown, well 16 is of type N.
The presence of well 16 reduces the thickness of epitaxial layer 10 in area 4 and, thereby, the parasitic conduction area between analog block 2 and digital block 3 (between transistors 12 and 13).
Most often, well 16 is biased by the positive supply of analog block 2 or of digital block 3 by means of a track 22 contacting a heavily-doped (N.sup.+) area 23, to reverse bias the well/substrate junction.
In FIG. 2, a full line 17 symbolizes a biasing of well 16 by the positive supply of digital block 3, and a dotted line 18 symbolizes the biasing of well 16 by the positive supply of analog block 2.
A disadvantage of such a solution is that the lateral stray capacitors C1, C2, and the vertical stray capacitor C3 of the PN junctions created by well 16 destroy the expected effect. Indeed, since supply voltage Vdd is corrupted by the switching noise of the digital part (the switching noise on the positive supply line and the ground lines are equivalent in spectrum and amplitude), this noise is carried by the junction stray capacitors of well 16.
If well 16 is biased by the power supply of the digital block (connection 17), noise coming from the power supply of block 3 is transmitted to the ground of the analog block through capacitors C1 (perimeter capacitor) and C3 (well bottom surface capacitor).
If well 16 is biased by the power supply of the analog block (connection 18), switching noise coming from the ground of digital block 3 corrupts the positive power supply of the analog block via capacitors C2 and C3.